US7078970B2 - CMOS class AB operational amplifier - Google Patents
CMOS class AB operational amplifier Download PDFInfo
- Publication number
- US7078970B2 US7078970B2 US10/901,707 US90170704A US7078970B2 US 7078970 B2 US7078970 B2 US 7078970B2 US 90170704 A US90170704 A US 90170704A US 7078970 B2 US7078970 B2 US 7078970B2
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- output
- driving
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/30—Single-ended push-pull [SEPP] amplifiers; Phase-splitters therefor
- H03F3/3001—Single-ended push-pull [SEPP] amplifiers; Phase-splitters therefor with field-effect transistors
- H03F3/3022—CMOS common source output SEPP amplifiers
- H03F3/3028—CMOS common source output SEPP amplifiers with symmetrical driving of the end stage
- H03F3/303—CMOS common source output SEPP amplifiers with symmetrical driving of the end stage using opamps as driving stages
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/30—Indexing scheme relating to single-ended push-pull [SEPP]; Phase-splitters therefor
- H03F2203/30021—A capacitor being coupled in a feedback circuit of a SEPP amplifier
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/30—Indexing scheme relating to single-ended push-pull [SEPP]; Phase-splitters therefor
- H03F2203/30036—A feedback circuit to stabilise the SEPP being used
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45644—Indexing scheme relating to differential amplifiers the LC comprising a cross coupling circuit, e.g. comprising two cross-coupled transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45658—Indexing scheme relating to differential amplifiers the LC comprising two diodes of current mirrors
Definitions
- the present invention relates to an operational amplifier in CMOS technology with a Class AB output stage having an output terminal and an input stage driving the output stage.
- the present invention provides an improved CMOS Class AB operational amplifier that can be used as a buffer and can operated within a wide range of supply voltages from the maximum voltage allowed by the technology used down to less than two MOSFET threshold voltages.
- the CMOS operational amplifier with a Class AB output stage has an output terminal and an input stage driving the output stage.
- the Class AB output stage includes a pair of p-channel and n-channel output transistors series-connected between the VDD and VSS supply terminals of a power supply.
- Each of the output transistors has associated driving and biasing circuitry with a pair of differential (positive and negative) driving inputs and a biasing input.
- the input stage has driving outputs connected to corresponding ones of the driving inputs of the output stage.
- Each driving output is derived from the drain of a MOS transistor connected in series with a diode connected MOS transistor between the VDD and VSS supply terminals.
- the op-amp can be operated over the full range of supply voltage.
- the input stage does not use a common source amplifier with a current mirror as load. Instead, the diode-connected transistors are used as load. These diode loads provide the correct dc operation point for the differential inputs of the output stage. The diode loads also reduce the gain, and improve the stability, of the input stage.
- the output of the op-amp can drive resistive loads efficiently as current source or current sink. Although a sufficient open loop gain (60 dB or more) can be achieved, the op-amp when used as a buffer remains stable at capacitive loads of 100 nF or more.
- An embodiment with an increased gain includes a resistor in series with each diode load.
- a further increase in gain is achieved in an embodiment with cross-coupled load transistors for the differential input transistors.
- FIG. 1 is a diagram of an output stage of the operational amplifier
- FIG. 2 is a diagram of an input stage of the operational amplifier
- FIG. 3 is a diagram of the entire operational amplifier with an optional nested Miller compensation.
- the output stage of a Class AB CMOS operational amplifier includes a p-channel output transistor MP 0 and an n-channel output transistor, the interconnected drains of which constitute the output of the circuit and the sources of which are connected to the VDD and VSS supply terminals, respectively.
- Transistor MP 0 has associated driving and biasing circuitry with a p-channel current mirror transistor MP 3 the source of which is connected to terminal VDD, the gate of which is connected to the gate of transistor MP 0 and the drain of which is connected to the interconnected sources of a pair of p-channel driver transistors MP 2 , MP 4 .
- the gates of driver transistors MP 2 and MP 4 form a pair of differential drive inputs VP 1 i and VP 2 i .
- Driver transistor MP 2 has its drain connected to terminal VSS and driver transistor MP 4 has its drain connected to the drain of an n-channel bias control transistor MN 4 , the gate of which forms a bias control input VNi and the source of which is connected to terminal VSS.
- the drains of transistors MP 4 and MN 4 are also connected to the gates of transistors MP 3 and MP 0 .
- driving and biasing circuitry is associated with output transistor MN 0 , but in a complementary conductivity type.
- the circuitry has n-channel driver transistors MN 2 , MN 3 , n-channel current mirror transistor MN 1 and p-channel bias control transistor MP 6 , with differential inputs VN 1 i and VN 2 i and bias control input Vpi.
- the input stage shown in FIG. 2 includes differential input n-channel transistors MN 11 and MN 12 with cross-coupled p-channel load transistors MP 13 , MP 14 and n-channel bias control transistor MN 10 .
- Differential inputs INP and INM are applied to the gates of transistors MN 11 and MN 12 .
- a diode connected n-channel transistor MN 14 receives a bias control current IBIAS on its drain and has its source connected to terminal VSS, providing a bias control signal VNo to the gate of transistor MN 10 .
- a second bias control signal VPo is provided at the interconnected drains of diode connected p-channel transistor MP 25 and n-channel current mirror transistor MN 22 .
- Diode connected p-channel transistors MP 36 and MP 37 are connected across the source and drain of transistors MP 14 and MP 13 , respectively.
- Differential output signals VN 1 o and VN 2 o are provided at the drains of p-channel transistors MP 19 and MP 20 , respectively.
- the gates of transistors MP 19 and MP 20 are connected to the drains of transistors MP 13 and MP 14 , respectively.
- Transistor MP 19 is connected in series with a resistor R 9 and a diode connected n-channel transistor MN 16 .
- transistor MP 20 is connected in series with a resistor R 6 and a diode connected n-channel transistor MN 17 .
- Differential output signals VP 1 o and VP 2 o are provided at the drains of n-channel transistors MN 21 and MN 19 , respectively.
- Transistor MN 21 is connected in series with a resistor R 2 and a diode connected p-channel transistor MP 23 .
- transistor MN 19 is connected in series with a resistor R 3 and a diode connected p-channel transistor MP 24 .
- the gate of transistor MN 21 is connected to the drain of inverter transistor MP 22 , a p-channel transistor that has its gate connected to the drain of transistor MP 14 and its source to terminal VDD, and that is connected in series with a diode connected n-channel transistor MN 20 .
- transistor MN 19 is connected to the drain of inverter transistor MP 21 , a p-channel transistor that has its gate connected to the drain of transistor MP 13 and its source to terminal VDD, and that is connected in series with a diode connected n-channel transistor MN 18 .
- each signal input VP 1 i , VP 2 i , VN 1 i , VN 2 i and VNi, VPi is connected with a corresponding signal output VP 1 o , VP 2 o , VN 1 o , VN 2 o and VNo, VPo.
- a nested Miller compensation is achieved with feedback capacitors C 0 , C 1 that are connected between the output of the amplifier and the gates of transistors MP 2 and MN 2 , respectively, and feedback capacitors C 2 , C 3 connected between the output of the amplifier and the interconnected drains of transistors MP 22 , MN 20 and transistors MP 21 and MN 18 , respectively.
- the Miller compensation is optional and depends on the capacitive load of the operational amplifier. Typically, a Miller compensation will be used at a low capacitive load of the order of 100 pF.
- the diode connected transistors MP 23 , MP 24 and MN 16 , MN 17 always provide the correct dc operation point for the differential inputs of the output stage, from the maximum voltage permitted with the technology used down to a low supply voltage less than twice a MOSFET threshold voltage.
Abstract
Description
Claims (6)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10335067.5 | 2003-07-31 | ||
DE10335067A DE10335067B4 (en) | 2003-07-31 | 2003-07-31 | operational amplifiers |
Publications (2)
Publication Number | Publication Date |
---|---|
US20050035822A1 US20050035822A1 (en) | 2005-02-17 |
US7078970B2 true US7078970B2 (en) | 2006-07-18 |
Family
ID=34129474
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/901,707 Active US7078970B2 (en) | 2003-07-31 | 2004-07-27 | CMOS class AB operational amplifier |
Country Status (2)
Country | Link |
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US (1) | US7078970B2 (en) |
DE (1) | DE10335067B4 (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080238546A1 (en) * | 2007-03-26 | 2008-10-02 | Hyoung Rae Kim | Fully differential class ab amplifier and amplifying method using single-ended, two-stage amplifier |
WO2008144722A2 (en) * | 2007-05-21 | 2008-11-27 | Texas Instruments Incorporated | Class ab output stage and method for providing wide supply voltage range |
WO2012009167A2 (en) * | 2010-07-13 | 2012-01-19 | Entropic Communications, Inc. | Method and apparatus for broadband input matching with noise and non-linearity cancellation in power amplifiers |
US20150214929A1 (en) * | 2014-01-29 | 2015-07-30 | Samsung Electro-Mechanics Co., Ltd. | Gate driver including level shifter and method for driving the same |
US20180234056A1 (en) * | 2016-06-06 | 2018-08-16 | Boe Technology Group Co., Ltd. | Two-stage operational amplifier |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7554405B2 (en) | 2007-05-02 | 2009-06-30 | Samsung Electronics Co., Ltd. | Adaptive biasing input stage and amplifiers including the same |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5917378A (en) * | 1997-06-27 | 1999-06-29 | Industrial Technology Research Institute | Rail-to-rail type of operational amplifier with a low offset voltage achieved by mixed compensation |
US20010024140A1 (en) * | 1999-12-02 | 2001-09-27 | Craig Taylor | Negative feedback amplifier circuit |
US6885240B2 (en) * | 2002-07-19 | 2005-04-26 | Hynix Semiconductor Inc. | Amplifying circuit with variable load drivability |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4480230A (en) * | 1983-07-05 | 1984-10-30 | National Semiconductor Corporation | Large swing CMOS power amplifier |
-
2003
- 2003-07-31 DE DE10335067A patent/DE10335067B4/en not_active Expired - Fee Related
-
2004
- 2004-07-27 US US10/901,707 patent/US7078970B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5917378A (en) * | 1997-06-27 | 1999-06-29 | Industrial Technology Research Institute | Rail-to-rail type of operational amplifier with a low offset voltage achieved by mixed compensation |
US20010024140A1 (en) * | 1999-12-02 | 2001-09-27 | Craig Taylor | Negative feedback amplifier circuit |
US6885240B2 (en) * | 2002-07-19 | 2005-04-26 | Hynix Semiconductor Inc. | Amplifying circuit with variable load drivability |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080238546A1 (en) * | 2007-03-26 | 2008-10-02 | Hyoung Rae Kim | Fully differential class ab amplifier and amplifying method using single-ended, two-stage amplifier |
US7586373B2 (en) | 2007-03-26 | 2009-09-08 | Samsung Electronics Co., Ltd. | Fully differential class AB amplifier and amplifying method using single-ended, two-stage amplifier |
WO2008144722A2 (en) * | 2007-05-21 | 2008-11-27 | Texas Instruments Incorporated | Class ab output stage and method for providing wide supply voltage range |
WO2008144722A3 (en) * | 2007-05-21 | 2009-01-22 | Texas Instruments Inc | Class ab output stage and method for providing wide supply voltage range |
WO2012009167A2 (en) * | 2010-07-13 | 2012-01-19 | Entropic Communications, Inc. | Method and apparatus for broadband input matching with noise and non-linearity cancellation in power amplifiers |
US8390378B2 (en) | 2010-07-13 | 2013-03-05 | Entropic Communications, Inc. | Method and apparatus for broadband input matching with noise and non-linearity cancellation in power amplifiers |
WO2012009167A3 (en) * | 2010-07-13 | 2014-03-20 | Entropic Communications, Inc. | Method and apparatus for broadband input matching with noise and non-linearity cancellation in power amplifiers |
US20150214929A1 (en) * | 2014-01-29 | 2015-07-30 | Samsung Electro-Mechanics Co., Ltd. | Gate driver including level shifter and method for driving the same |
US20180234056A1 (en) * | 2016-06-06 | 2018-08-16 | Boe Technology Group Co., Ltd. | Two-stage operational amplifier |
US10404220B2 (en) * | 2016-06-06 | 2019-09-03 | Boe Technology Group Co., Ltd. | Two-stage operational amplifier |
Also Published As
Publication number | Publication date |
---|---|
DE10335067A1 (en) | 2005-03-10 |
DE10335067B4 (en) | 2007-09-27 |
US20050035822A1 (en) | 2005-02-17 |
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