Differential amplifier for measuring Hall voltage

Initially (there is some unwanted difference here, of 0.2V. This is a
problem):
---------o V3 = 5.1V
| |
|sample|
| |
---------o V4 = 4.9V

After applying the magnetic field (a Hall voltage of 0.01mV can now be
seen):
---------o V3 = 5.10001V
| |
|sample|
| |
---------o V4 = 4.89999V

Here's the circuit:

---------o V3 --> High Z Buffer --- |\ differential
| | |---> | \amplifier gain = 1
|sample| | |--> Vout = 0.00001V
| | |---> | /
---------o V4 --> High Z Buffer --- |/

I just need some circuitry between the buffers and the diff. amp. or
after the diff. amp which can accurately and reliably tune the output to
zero (within precision <1 mV hopefully) before doing a measurement. Can
anyone tell me of a slick way to do this? If anyone can also suggest
some op-amps to use, that would be cool as well, although I already have
some in mind. The resistance of my sample is about 10^13 ohms. Thanks
for any help.

David

Well, using gain of one as shown only increases the noise and adds in
thermoelectric problems also.
Try a gain of 100 in the hiZ buffers and make them differential so
that you can subtract out 5.0000V.
This gives a "worst case" 10V output.
Now if those initial values are repeatable and reliable, then subtract
out the 5.1V and the 4.9V respectively, making for a difference of zero.
Then make the final differencing amplifier a gain of 100, which
results in a theoretical 100mV.
Be damn careful about shielding, use of driven shields, same metals,
isothermal layouts, etc.

What you are describing is pretty close to an instrumentation
amplifier, except that they provide differential gain as well as
offset adjustment. They also often include provision for signal
follower outputs that are used to drive the shields of the input
lines. I am not sure you will find one that handles 10^13 resistance
sources, though. This is a very high resistance for a Hall effect
source.

http://www.elektr.polsl.gliwice.pl/~jelon/INA_110.pdf
--
John Popelish

On Tue, 02 Dec 2003 00:28:21 -0500, DG <david.gra...@telus.net>
wrote:

If I were of a suspicious nature, I'd say this was a Troll.

Do you really mean your useable signal is in the range 10 to 100uV,
(that's micro-volts)? If so, you have problems. Just to put things
in perspective, to achieve a modest 10% measurement accuracy in your
minimum signal of interest, you can afford a maximum error, referred
to the input, of 1uV.

Taking the performance of the diff-amp to start with, you need to
remove nominally 5V to an accuracy of at least 1uV; or, put another
way, you need a CMMR of better than 130db. I agree with Robert that
you need to apply some gain before the diff amp, but, with a possible
differential signal of up 0.2V, a gain of 100 is too high. (Introduce
gain with the conventional three-amplifier instrumentation
configuration).

Let's say you add a gain of 30db; that reduces the CMMR requirement of
the diff-amp to something over 100db, whilst leaving reasonable
headroom at the outputs of the two front-end amps. I've had a quick
look at what's available and that exceeds the performance of any
monolithic part I've so far come across. I've also just done a quick
calculation and to do it discretely would require resistor matching
to better than 0.00005% - certainly not off the shelf parts. (Linear
Technology do claim a CMMR in excess of 120bd for an instrumentation
amplifier based around their LTC1043 'Switched Capacitor Building
Block', but I can't vouch for this, nor do I know if this part is
still available).

Next there's the issue of removing the unwanted differential signal of
up to 0.2V, again to within 1uV or better referred to the input. I
personally wouldn't consider trying this until the signal was
single-ended, but, wherever you do it, that's an accuracy/stability
requirement of 0.0005%. Two ways to remove the unwanted signal spring
to mind:

Sample-and-hold whilst input signal is zeroed, then subtract SAH
output from subsequent measurements. If you're going to do this, you
need to be able to repeat the process often enough so that the droop
in the SAH doesn't stray outside the required accuracy.
Alternatively, digitise the signals and remove the offset digitally,
(requires better than 17-bit resolution).

Either way, the accuracy required is demanding, to put it mildly.

Finally: I can't believe the 10^13 ohms source resistance isn't a
typo? If it's not, you're going to require some form of bias current
cancellation and an offset current performance in the two buffers
equivalent to better than an 10^-19A, (0.1 atto-amps I believe).
That's one hell of an amplifier - I would guess, several orders of
magnitude beyond state-of-the-art capability!

Not to mention issues of long-term/temperature stability. This, plus
the other issues that Robert mentioned, puts me in mind of the
Irishman who, when asked by a tourist for directions to some beauty
spot, thought for a moment and then replied:

'To be sure, I wouldn't be startin from here if I were you'.

I wish you luck.

Regards

Ted Wilson

PS I've just re-read your post and spotted that common-mode
voltage can be as high as 20V and the unwanted differential signal as
high as 1V, which makes things significantly worse than I've allowed
for.

How about getting rid of the common mode voltage, then doing the
"tare" digitally using something like a 20-bit ADC?

The 10^13 ohms sounds like the real bear. A 10% (1uV) error at 10^13
ohms is a current of 10^-19A- less than 1 electron per second- clearly
in the realm of physics rather than electronics. Consider also the
settling time into any input capacitance.

Best regards,
Spehro Pefhany
--
"it's the network..." "The Journey is the reward"
sp...@interlog.com Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog Info for designers: http://www.speff.com

I'm glad you realized it wasn't a Troll, and thanks for replying.

I was going really worst-case with that signal. I expect 100uV.

Yes, I've already thought of this CMRR problem in the diff. amp. I also
figured at least 120 or more dB. I've looked at the LT1008 which has
114 dB guaranteed, up to 130dB typical. Also the LT1024AM has good
CMRR. Jim Williams claims 160dB in the app note
http://www.linear.com/pdf/an6.pdf which uses a system similar to the
LTC1043 that you found, but with some opto-couplers

I'm starting to realize it might be worse than I thought.

The sample is amorphous silicon. The volume conductivity is usually
around 10^10 (Ohm*cm). The film thickness is about 1um, or 10^-4 cm, so
the sheet resistance is about 10^14. So I guess it's even more than I
thought. Maybe I should use a thicker film, 10um to help things.

I thought that the Hall effect of amorphous silicon had been measured
before, as early as the 1970s or maybe 60s as well. I'll have to go
look at my papers again. Many times they use doped amorphous silicon,
which of course will affect the mobility and hence the Hall voltage, but
this is done sometimes. Maybe they always use doped a-Si instead
because intrinsic a-Si to to resistive.

Why 10^-19 A?

Yes this is a problem I think. We have no vacuum or temperature
controlled chamber right now, which will suck.

DG wrote:

My idea was correct. I looked through my stack of 20 papers or so and
after looking through less than half of them, I realized that they
always used DOPED a-Si, or microcrystalline silicon (which easily
absorbs oxygen, and n-type donor). They are sometimes kind of sneaky
about it, for example the title of the paper will be "Hall effect in
amorphous silicon", yet it mentions in the paper that the samples are
doped. Since the mobility surely changes in a doped sample (although by
a very small amount) it would be more aptly titled "Hall effect in
phosphorous-doped amorphous silicon". I can't believe I was fooled.

Well, I will still have some of the issues, the voltage level is the
same as it is related to the Hall mobility which is still low, around
0.1 cm^2/V*s which gives a Hall voltage of 0.2 mV, so +0.1 mV on V3 and
-0.1 mV on V4. In the worst case the mobility would be 0.01 cm^2/V*s
which gives half of that, so 50 uV on V3 and V4. I still have the CMRR
issue, as well as all the other issues. Only the 10^-19 A issue is gone
I guess.

Dave

DG wrote:

Ted, do you have any opinion about the circuit in the URL above for my
application? I've never used optoisolators before, although I
understand how this circuit works completely, and I found some FET
couplers like these from Fairchild:
http://www.fairchildsemi.com/ds/H1/H11F1.pdf

The only thing I'm worried about is keeping 1uV or thereabouts
resolution. Although amplifying the signal before this diff. amp. step
helps in that regard I guess. I'm still wrapping my head around how to
remove the unwanted 0.1V offset. And if I remove that offset at the
input, then I should be able to also remove the 5V common-mode signal as
well. Although I think you said, you'd rather remove the 0.1V unwanted
offset on the single-ended side. Thanks a lot for your help.

David

So, what is wrong with a DIY similar to what i mentioned, but the two
gain buffers are FET or BICMOS or other low input current devices?
Connect them as times +100 followers, low side of gain divider goes to
the offset voltage.
One still has a guard voltage available on the divider.

I mostly understand what you are saying, but I'm confused about how
where the guard voltage can be taken from. I thought the guard voltage
had to be taken from a x1 follower?

BTW, when you say +100 follower I assume you mean an opamp in
non-inverting configuration with a gain of 100. I just always thought
the word "follower" was only used to describe something with gain=1, but
maybe you use "follower" to describe something non-inverting.

When you say "gain divider" you mean the voltage divider which connects
the output to the negative input for the feedback right? I'm sorry I
don't know all the terminology, unfortunately they don't teach us that
in school... So we connect the offset voltage (5-10V let's say) to the
bottom of that voltage divider, and we can take the guard from the
negative input of the opamp? I am right?

I know your method works, but I can't get the equations right. The
output should be:

Vout = (Vpos - Voffset)*(1+R2/R1)

where Vpos is the voltage at the positive terminal of opamp and Vneg is
at the negativ terminal of opamp but I'm not getting that. I get that
the current from Vneg to Voffset is I1=(Vneg-Voffset)/R1. So Vout = I1
+ Vneg. Therefore vout = Vpos(1+R2/R1) - Voffset(R2/R1), where I
replaced Vneg with Vpos since they should be the same.

Thanks for your help.

Robert Baer wrote:

If I use the circuit shown here: http://www.linear.com/pdf/an6.pdf with
two highZ buffers in front, for guarding and perhaps some gain, then
would I get the same performance? Using the offset removal method you
suggested, it may require that I zero the output by adjusting the
offset, frequently, and I also need to have really good precision with
the zeroing. If that signal drifts at all that could be a problem as
well. I think maybe the circuit in the app note avoids this problem.

Thanks,
Dave

If I use a 24-bit ADC for example, will I actually be able to get
Vref/2^24 volts resolution? So if the reference voltage is ten volts,
can I get 0.5 uV resolution? Obviously not I think. So what is the
typical bottom range for ADCs? I think we have a PCI ADC card in our
lab, I'm not sure how many bits it has though.

I played around recently with a 24 bit ADC. It was a Burr Brown
ADS1252 sigma-delta type. It was indeed able to achieve a true 24 bit
resolution (with some averaging), as per the datasheet. In fact I
believe I got up to 26 bits at one point!

<http://focus.ti.com/docs/prod/folders/print/ads1252.html>

<http://www-s.ti.com/sc/ds/ads1252.pdf>

--

John Devereux

Did you measure response times? Resolution vs averaging time?
Settling time - step response to 20, 22 and 24 bits, etc.?

Thanks,
- Win

whill_at_picovolt-dot-com

Hello David

Sorry for the delay coming back to you. I'm having to post this response
through Outlook Express, which is something I avoid these days, not least
because postings here more often than not can't be seen from Google, which
is what I usually use. For some reason, this thread is glacially slow
appearing on Google Groups and today, (Thursday), I can see only the first
three posts there, (up to and including John Popelish's), which were posted
back on Monday. I couldn't even access the group from home last night!

Anyway, a couple of points:

The LT1008 and 1024 are not differential amplifiers as is meant in this
context and the CMMR quoted in the data sheets is simply that of the bare
amplifiers with their inverting and non-inverting inputs tied together and a
common voltage applied.

In order to convert a differential input into single ended, you
traditionally require the addition of four resistors around a basic
diff-amp, and the CMMR performance of the composite amplifier is invariably
dominated by the matching of these resistors. Burr Brown's INA105 is one
such device and has a guaranteed overall CMMR of 86db, which falls somewhat
short of your requirement.

I've had a look at the Linear Tech App. Note and have a couple of comments:

The text refers to the use of opto-coupled MOSFETs, though it doesn't quote
a part number that I can find. It does however say that "switch leakage
typically rises above 1nA over 100V, . . ." which implies an off-resistance
greater than 10^11 ohms at voltages below 100V. Compare that with the 300M
ohms of the FET part you propose and you can see that there's a problem;
Take the case where S1 and S2 are ON and S3 and S4 OFF. S4 we are not
unduly worried about, since it connects to 0V, but, with +5V on the
left-hand end of S3, there's a current of around 16nA into the 0.2uF cap and
the inverting input of the amplifier, which is going to drive it +ve at a
rate of around 80mV/s - an unacceptable error for your application.

So, you are either going to have to find a better opto-switch, or add to the
circuit from the app note, to contend with the limited off-resistance of the
Fairchild parts. Off the top of my head, I'd suggest something along the
lines of splitting S3 into two series switches, both controlled by the
"read" signal, with the junction of the two switches bootstrapped to a
buffered version of the voltage on the LT1001's non-inverting input during
the 'off' period for S3. (This of course means another addition of another
switch, driven with the inverse of the "read" signal.

With a bit of ingenuity and some careful attention to detail in layout and
implementation, I reckon you should be able to achieve a CMMR that will
serve your purposes and, using a suitable A-D, you ought to be able to
remove the offset to the required level of accuracy.

The show-stopper is still the front end and the output resistance of these
Hall devices you are using.

If I have understood your responses to my post correctly, you have been able
to increase your minimum signal from 10 to 50uV, which is going to help, but
I couldn't see any reference to reduction in output resistance and, unless
something can be done to dramatically reduce that, I can't see you being in
with a prayer.

The 10^-19A offset requirement derived from the need to keep errors down to
the order of 1uV with a source of 10^13 ohms. Increasing your minimum
signal requirement means you can consider increasing the 1uV figure, but
bear in mind that the analysis in my original post was not rigorous and the
calculations I did were to achieve a 10% measurement error, based on one
source of error at a time, in order to get a feel for the scale of the
problem. In a working system, you are going to have to achieve your
required accuracy in the presence of the sum of all your sources of error,
so individual errors need to smaller that we've so far considered.

I had a look on the net for "ultra-low input current amplifiers" - by no
means a comprehensive trawl, but the best I could come up with was Nat
Semi's LMC6001 - 25fA part. They quote a typical offset current of 5fA,
(that's 5E-15A), for this device, but that's still a factor of 50000 adrift
of what's needed with 10^13 ohms. I haven't mentioned input offset voltage
yet, but just look at the spec for the LMC6001 - 350uV is the best figure I
can find and that's 350 times too big. (Another aspect of your problem is
going to be that the amplifiers with the lowest bias/offset currents don't
have the best offset voltage specs).

I'm sending you this direct by e-mail as well as posting, since I can't be
sure you'll see it in the group. Feel free to e-mail me with any questions,
but, if I were you, I'd keep this in the public domain for now - there are a
number of very clever guys out there with very specialised knowledge that
could be relevant to you problem and I think you're going to need all the
help you can get!

Hope some of this helps

Regards

Ted Wilson

Real 20 bits or even a bit more from a "24 bit" ADC is quite doable.
There are actually more (generally useless) bits available than the
nominal number in many of them. Burr-Brown (TI) provides curves that
show you how many real bits you're getting depending on operating
conditions, and others (LTC etc.) may do so as well. Noise is maybe
1-2ppm FS. Beyond that it depends on the part, on sample rate and
clock, whether you're using the internal input buffer (if it exists)
or not, and whether you're using the PGA (if it exists) or not.

The really high resolutions were only obtained by averaging over a
large fraction of a second. For example 25 bits at 65536 samples at
40kHz.

IIRC the thing starts of with ~19 "effective" bits for single samples.

You then need to average 4 times as many samples for each extra bit of
"resolution" (read "stability").

The "response time" ("latency") is about 5 or 6 samples I think.

What I did was use a bridge made of precision resistors, fed from the
VREF voltage (which was just the analog supply rail).

----------------------------------------- VREF
| | ___|__
R R |
| |----------------|+ ADS1252
| | |
|--------|----------------|-
R R |______
| | |
------------------------------------------ 0V

This simple arrangement gave the very high resolutions I saw.

--

John Devereux

> snip<

The part number quoted is the OFM-1A from Theta-J Corp.
I can't find them on the web, or that part number any more.

I think you will be up against "too hard to measure" for specs
on switches - for example the Aromat AQY221N2S specs
typical leakage of 0.01nA, but max is 10nA (which translates
to "we don't want to measure it in production"). This is a
photo-MOS relay like the OFM-1A, but loweer voltage rating.
Similarly, going to a reed relay, you get specs of "minimum 10^12
ohms",
but no typical.

Regards
Ian

[snip]

The penny dropped whilst I was walking the dogs this morning. Here I
am prattling about amplfier offsets of 350mV whilst discussing the
removal of up to 200mV in the previous paragraph. Okay, so there's
still the stability issue, but that's going to be dominated by drift
in the 200mV anyway.

Also, I notice I seem to have invented a new differential-amplifier
parameter - the "CMMR". What's that about then?

Doh!

Ted Wilson